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ltc3731h 3731hfb typical a pplica t ion fea t ures descrip t ion 3-phase, 600khz, synchronous buck switching regulator controller the ltc ? 3731h is a polyphase ? synchronous step-down switching regulator controller that drives all n-channel external power mosfet stages in a phase-lockable fixed frequency architecture. the ltc3731h is rated for operation up to 140c junction temperature. the 3-phase controller drives its output stages with 120 phase separation at frequencies up to 680khz per phase to minimize the rms current losses in both the input and output filter capacitors. the 3 - phase technique effectively triples the fundamental frequency, improving transient response while operating each controller at an optimal frequency for efficiency and ease of thermal design. light load efficiency is optimized by using a choice of output stage shedding or burst mode operation. the precision reference supports output voltages from 0.6v to 6v. current foldback provides protection for the external mosfets under short-circuit or overload condi- tions. please refer to the ltc3731 data sheet for 0c to 70c and C40c to 85c rated versions. l , lt, ltc, ltm, linear technology, the linear logo, burst mode, opti-loop and polyphase are registered trademarks and stage shedding is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents including 5481178, 5929620, 6177787, 6144194, 6100678, 5408150, 6580258, 6462525, 6304066, 5705919. figure 1. high current triple phase step-down converter a pplica t ions n 3-phase current mode controller with onboard mosfet drivers n 5% output current matching optimizes thermal performance and size of inductors and mosfets n 2% v ref accuracy over temperature up to 140c n reduced power supply induced noise n 10% power good output indicator n 225khz to 680khz per phase, pll, fixed frequency n pwm, stage shedding? or burst mode ? operation n opti-loop ? compensation minimizes c out n adjustable soft-start current ramping n short-circuit shutdown timer with defeat option n overvoltage soft latch n adjustable undervoltage lockout threshold n selectable phase output for up to 12-phase operation n available in 36-pin narrow (0.209") ssop and 5mm 5mm qfn packages n automotive and industrial power supplies n high output current dc/dc power supplies v in 0.003 0.8h 22f 35v 0.003 0.8h v in 0.003 c out 470f 4v v out 1.35v 55a v in 5v to 28v 0.8h v in 3731h f01 tg1 v cc 0.1f sw3 sw2 sw1 sw1 bg1 sense1 + sense1 ? boost1 boost2 boost3 tg2 sw2 bg2 pgood pllin pllfltr i th 0.01f 680pf 5k optional sync in power good indicator run/ss sgnd eain pgnd uvadj sense2 + sense2 ? tg3 sw3 bg3 sense3 + sense3 ? + 10f v cc 4.5v to 7v + ltc3731h 36k 12k 7.5k 100pf 6.04k efficiency vs i out efficiency (%) 0.1 load current (a) 100 90 80 70 60 50 40 30 20 10 0 1 10 100 3731h f01b v in = 8v v out = 1.5v v fcb = open v fcb = 5v v fcb = 0v
ltc3731h 3731hfb a bsolu t e maxi m u m r a t ings topside driver voltages (boost n ) ............ 38v to C0.3v switch voltage (sw n ) ................................... 32v to C5v boosted driver voltage (boost n C sw n ) .... 7v to C0.3v peak output current <1ms (tg n , bg n ) .......................5a supply voltages (v cc , v dr ), pgood pin voltage ................................................... 7v to C0.3v run/ss, pllfltr, pllin, uvadj, fcb voltages ..............................................v cc to C0.3v (note 1) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 top view g package 36-lead plastic ssop 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 v cc pllin pllfltr fcb nc nc nc eain sgnd sense1 + sense1 ? sense2 + sense2 ? sense3 ? sense3 + run/ss i th uvadj clkout pgood boost1 tg1 sw1 boost2 tg2 sw2 v dr bg1 pgnd bg2 bg3 sw3 tg3 boost3 phasmd sgnd t jmax = 140c, ja = 70c/w, jc = 25c/w pins 5 and 6 can be grounded or nc pin 7 must be left as nc 32 33 sgnd 31 30 29 28 27 26 25 9 10 11 12 top view uh package 32-lead (5mm s 5mm) plastic qfn 13 14 15 16 17 18 19 20 21 22 23 24 8 7 6 5 4 3 2 1nc nc eain sense1 + sense1 ? sense2 + sense2 ? sense3 ? boost2 tg2 sw2 v cc bg1 pgnd bg2 bg3 nc fcb pllfltr pllin clkout boost1 tg1 sw1 sense3 + run/ss i th uvadj phasmd/pg boost3 tg3 sw3 t jmax = 125c, ja = 34c/w, jc = 3c/w exposed pad (pin 33) is sgnd, must be soldered to pcb pins 1, 2 and 32 must be left as nc p in c on f igura t ion o r d er i n f or m a t ion lead free finish tape and reel part marking package description temperature range ltc3731hg#pbf ltc3731hg#trpbf ltc3731hg 36-lead plastic ssop C40c to 140c ltc3731huh#pbf ltc3731huh#trpbf 3731 32-lead (5mm 5mm) plastic qfn C40c to 140c consult ltc marketing for parts specified with wider operating temperature ranges. consult ltc marketing for information on non-standard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ sense + , sense C voltages ........................ 5.5v to C0.3v i th voltage ............................................... 2.4v to C0.3v operating junction temperature range (note 2) .................. C40c to 140c storage temperature range .................. C65c to 150c lead temperature g package (soldering, 10sec) .. 300c
ltc3731h 3731hfb e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v cc = v run/ss = 5v unless otherwise noted. symbol parameter conditions min typ max units main control loop v regulated regulated voltage at eain v ith = 1.2v (note 3) l 0.594 0.590 0.600 0.600 0.606 0.614 v v v sensemax maximum current sense threshold v eain = 0.5v, v ith open, v sense1 C , v sense2 C , v sense3 C = 0.6v, 1.8v l 65 60 75 75 85 90 mv mv i match maximum current threshold match worst-case error at v sensemax C5 5 % v loadreg output voltage load regulation (note 3) measured in servo loop, ?i th voltage = 1.2v to 0.7v measured in servo loop, ?i th voltage = 1.2v to 2v l l 0.1 C0.1 0.7 C0.7 % % v reflnreg output voltage line regulation v cc = 4.5v to 7v 0.03 %/v g m transconductance amplifier g m i th = 1.2v, sink/source 25a (note 3) l 3 5 7 mmho g mol transconductance amplifier gbw i th = 1.2v (g m ? z l , z l = series 1k C 100k C 1nf) 3 mhz v fcb forced continuous threshold l 0.54 0.60 0.66 v i fcb fcb bias current v fcb = 0.65v 0.2 0.7 a v binhibit burst inhibit threshold measured at fcb pin v cc C 1.5 v cc C 0.7 v cc C 0.3 v uvr undervoltage run/ss reset v cc lowered until the run/ss pin is pulled low 3.3 3.8 4.5 v uvadj undervoltage lockout threshold 1.13 1.18 1.23 v i uvadj undervoltage bias current at uvadj threshold 0.2 50 na i q input dc supply current normal mode shutdown (note 4) v cc = 5v v run/ss = 0v 2.3 50 3.5 100 ma a i run/ss soft-start charge current v run/ss = 1.9v C0.8 C1.5 C2.5 a v run/ss run/ss pin on threshold v run/ss , ramping positive 1 1.5 1.9 v v run/ssarm run/ss pin arming threshold v run/ss , ramping positive until short-circuit latch-off is armed 3.8 4.5 v v run/sslo run/ss pin latch-off threshold v run/ss , ramping negative 3.2 v i scl run/ss discharge current soft-short condition v eain = 0.375v, v run/ss = 4.5v C5 C1.5 a i sdlho shutdown latch disable current v eain = 0.375v, v run/ss = 4.5v 1.5 5 a i sense sense pins source current sense1 + , sense1 C , sense2 + , sense2 C , sense3 + , sense3 C all equal 1.2v; current at each pin 13 20 a df max maximum duty factor in dropout, v sensemax 30mv 95 98.5 % tg t r , t f top gate rise time top gate fall time c load = 3300pf c load = 3300pf 30 40 90 90 ns ns bg t r , t f bottom gate rise time bottom gate fall time c load = 3300pf c load = 3300pf 30 20 90 90 ns ns tg/bg t 1d top gate off to bottom gate on delay synchronous switch-on delay time all controllers, c load = 3300pf each driver 50 ns bg/tg t 2d bottom gate off to top gate on delay top switch-on delay time all controllers, c load = 3300pf each driver 60 ns t on(min) minimum on-time tested with a square wave (note 5) 110 ns
ltc3731h 3731hfb note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the ltc3731h is guaranteed to meet specifications over the C40c to 140c operating junction temperature range. note that the maximum ambient temperature is determined by specific operating conditions in conjunction with board layout, the rated package thermal resistance and other environmental factors. junction temperature (t j ) is calculated from the ambient temperature t a and power dissipation pd according to the following formula: l tc3731hg: t j = t a + (p d ? 70c/w) ltc3731hg: t j = t case + (p d ? 25c/w) ltc3731huh: t j = t a + (p d ? 34c/w) high junction temperatures degrade operating lifetimes. operating lifetime at junction temperatures greater than 125c is derated to 1000 hours. the ltc3731h is tested under pulsed load conditions such that t j t a . e lec t rical c harac t eris t ics symbol parameter conditions min typ max units power good output indication v pgl pgood voltage output low i pgood = 2ma, g package i pgood = 1.6ma, uh package 0.1 0.5 0.3 1 v v i pgood pgood output leakage v pgood = 5v 1 a v pgthneg v pgthpos pgood trip thresholds v eain ramping negative v eain ramping positive v eain with respect to set output voltage, pgood goes low after v uvdly delay C7 7 C10 10 C13 13 % % v pgdly power good fault report delay after v eain is forced outside the pgood thresholds 100 150 s oscillator and phase-locked loop f nom nominal frequency v pllfltr = 1.2v 360 400 440 khz f low lowest frequency v pllfltr = 0v 190 225 260 khz f high highest frequency v pllfltr = 2.4v 600 680 750 khz v pllth pllin input threshold minimum pulse width > 100ns 1 v r pllin pllin input resistance 50 k i pllfltr phase detector output current sinking capability sour cing capability f pllin < f osc f pllin > f osc 20 20 a a r relphs controller 2-controller 1 phase controller 3-controller 1 phase 120 240 deg deg clkout controller 1 tg to clkout phase phasmd = 0v phasmd = 5v 30 60 deg deg the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v cc = v run/ss = 5v unless otherwise noted. note 3: the ic is tested in a feedback loop that servoes the error amplifier output voltage to its midrange point (v ith = 1.2v). note 4: dynamic supply current is higher due to the gate charge being delivered at the switching frequency. see applications information. note 5: the minimum on-time condition corresponds to an inductor peak-to-peak ripple current of 40% of i max (see minimum on-time considerations in the applications information section). note 6: this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. overtemperature protection becomes active at a junction temperature greater than the maximum operating temperature. continuous operation above the specified maximum operating junction temperature may impair device reliability.
ltc3731h 3731hfb typical p er f or m ance c harac t eris t ics reference voltage vs temperature error amplifier g m vs temperature maximum i sense threshold vs temperature oscillator frequency vs temperature operating frequency vs v pllfltr undervoltage reset voltage vs temperature efficiency vs i out (figure 14) efficiency vs v in (figure 14) efficiency vs frequency (figure 14) efficiency (%) 0.1 load current (a) 100 90 80 70 60 50 40 30 20 10 0 1 10 100 3731h g01 v in = 8v v out = 1.5v v fcb = open v fcb = 5v v fcb = 0v v in (v) 0 efficiency (%) 100 95 90 85 80 75 70 65 60 55 50 20 3731h g02 5 10 15 25 i l = 45a i l = 15a v out = 1.5v f = 225khz frequency (khz) 200 efficiency (%) 100 95 90 85 80 75 600 3731h g03 300 400 500 i load = 20a v out = 1.5v v in = 20v v in = 12v v in = 8v v in = 5v temperature (c) ?50 reference voltage (mv) 3731h g04 0 25 50 75 610 605 600 595 590 ?25 150125100 temperature (c) 4.0 error amplifier g m (mmho) 4.5 5.5 6.0 3731h g05 5.0 ?50 0 25 50 75 ?25 150125100 ?50 0 25 50 75 ?25 150125100 temperature (c) 3731h g06 maximum i sense threshold (mv) 85 80 75 70 65 v o = 1.75v v o = 0.6v ?50 0 25 50 75 ?25 150125100 temperature (c) frequency (khz) 700 600 500 400 300 200 100 0 3731h g07 v pllfltr = 2.4v v pllfltr = 1.2v v pllfltr = 0v v pllfltr = 5v pllfltr pin voltage (v) 0 operating frequency (khz) 700 600 500 400 300 200 0.5 1 1.5 2 2.5 3731h g08 ?50 0 25 50 75 ?25 150125100 temperature (c) 3731h g09 0 under voltage reset (v) 1 3 4 5 2
ltc3731h 3731hfb typical p er f or m ance c harac t eris t ics maximum i sense vs v run/ss maximum current sense threshold vs duty factor peak current threshold vs v ith percentage of nominal output vs peak i sense (foldback) maximum duty factor vs temperature i sense pin current vs v out short-circuit arming and latchoff vs temperature supply current vs temperature run/ss pull-up current vs temperature ?50 0 25 50 75 ?25 150125100 0 run/ss pin voltage (v) 1 3 4 5 2 temperature (c) 3731h g10 arming latchoff ?50 0 25 50 75 ?25 150125100 0 supply current (ma) shutdown current (a) 0.4 2.0 1.6 2.4 2.8 1.2 0.8 temperature (c) 3731h g11 100 80 60 40 20 0 v cc = 5v ?50 0 25 50 75 ?25 150125100 0 run/ss pullup current (a) 0.5 1.5 2.0 3.0 2.5 1.0 temperature (c) 3731h g12 v run/ss = 1.9v v run/ss voltage (v) 0 maximum i sense (mv) 80 70 60 50 40 30 20 10 0 4 3731h g13 1 2 3 5 6 duty factor (%) 0 0 i sense voltage (mv) 25 50 75 20 40 60 80 3731h g14 100 v ith (v) 0 i sense voltage threshold (mv) 75 60 45 30 15 0 ?15 0.6 1.2 1.8 2.4 3731h g15 percentage of nominal output voltage (%) 0 peak i sense voltage (mv) 80 70 60 50 40 30 20 10 0 80 3731h g16 2010 30 50 70 90 40 60 100 ?50 0 25 50 75 ?25 150125100 90 maximum duty factor (%) 92 96 98 100 94 temperature (c) 3731h g17 v pllfltr = 0v v out (v) 0 i sense pin current (a) 40 30 20 10 0 ?10 ?20 ?30 3731h g18 2 5 1 3 4
ltc3731h 3731hfb typical p er f or m ance c harac t eris t ics continuous mode at 1 amp, light load current (circuit of figure 14) transient load current response: 0 amp to 50 amp (circuit of figure 14) shed mode at 1 amp, light load current (circuit of figure 14) burst mode at 1 amp, light load current (circuit of figure 14) 3731h g20 v in = 12v v out = 1.5v v fcb = v cc frequency = 225khz v out ac, 20mv/div v sw1 10v/div v sw2 10v/div v sw3 10v/div 4s/div 3731h g21 v in = 12v v out = 1.5v v fcb = open frequency = 225khz v out ac, 20mv/div v sw1 10v/div v sw2 10v/div v sw3 10v/div 4s/div 3731h g22 v in = 12v v out = 1.5v v fcb = 0v frequency = 225khz v out ac, 20mv/div v sw1 10v/div v sw2 10v/div v sw3 10v/div 4s/div 3731h g23 v in = 12v v out = 1.5v v fcb = v cc frequency = 225khz v out ac, 20mv/div i load 20a/div 20s/div
ltc3731h 3731hfb p in func t ions bg1 to bg3: high current gate drives for bottom n - channel mosfets. voltage swing at these pins is from ground to v cc . boost1 to boost3: positive supply pins to the topside floating drivers. bootstrapped capacitors, charged with external schottky diodes and a boost voltage source, are connected between the boost and sw pins. voltage swing at the boost pins is from boost source voltage (typically v cc ) to this boost source voltage + v in (where v in is the external mosfet supply rail). clkout: output clock signal available to synchronize other controller ics for additional mosfet stages/phases. eain: this is the input to the error amplifier that com- pares the feedback voltage to the internal 0.6v reference voltage. fcb: forced continuous control input. the voltage ap- plied to this pin sets the operating mode of the controller. the forced continuous current mode is active when the applied voltage is less than 0.6v. burst mode operation will be active when the pin is allowed to float and a stage shedding mode will be active if the pin is tied to the v cc pin. (do not apply voltage directly to this pin prior to the application of voltage on the v cc pin.) pgood: this open-drain output is pulled low when the output voltage has been outside the pgood tolerance window for the v pgdly delay of approximately 100s. i th : error amplifier output and switching regulator com- pensation point. all three current comparators thresholds increase with this control voltage. pgnd: driver power ground. this pin connects directly to the sources of the bottom n-channel external mosfets and the (C) terminals of c in . phasmd: this pin determines the phase shift between the first controllers rising tg signal and the rising edge of the clkout signal. logic 0 yields 30 degrees and logic 1 yields 60 degrees. pllin: synchronization input to phase detector. this pin is internally terminated to sgnd with 50k. the phase-locked loop will force the rising top gate signal of controller 1 to be synchronized with the rising edge of the pllin signal. pllfltr: the phase-locked loops lowpass filter is tied to this pin. alternatively, this pin can be driven with an ac or dc voltage source to vary the frequency of the internal oscillator. (do not apply voltage directly to this pin prior to the application of voltage on the v cc pin.) run/ss: combination of soft-start, run control input and short-circuit detection timer. a capacitor to ground at this pin sets the ramp time to full current output as well as the time delay prior to an output voltage short-circuit shutdown. a minimum value of 0.01f is recommended on this pin. sense1 + , sense2 + , sense3 + , sense1 C , sense2 C , sense3 C : the inputs to each differential current com- parator. the i th pin voltage and built-in offsets between sense C and sense + pins, in conjunction with r sense , set the current trip threshold level. sgnd: signal ground. this pin must be routed sepa- rately under the ic to the pgnd pin and then to the main ground plane. the exposed pad in the uh package must be soldered to pcb ground for electrical contact and rated thermal performance. sw1 to sw3: switch node connections to inductors. voltage swing at these pins is from a schottky diode (external) voltage drop below ground to v in (where v in is the external mosfet supply rail). tg1 to tg3: high current gate drives for top n-channel mosfets. these are the outputs of floating drivers with a voltage swing equal to the boost voltage source super- imposed on the switch node voltage sw. uvadj: input to the undervoltage shutdown compara- tor. when the applied input voltage is less than 1.2v, this comparator turns off the output mosfet driver stages and discharges the run/ss capacitor. v cc : main supply pin. because this pin supplies both the controller circuit power as well as the high power pulses supplied to drive the external mosfet gates, this pin needs to be very carefully and closely decoupled to the ics pgnd pin. vdr: supplies power to the bottom gate drivers only. this pin needs to be very carefully and closely decoupled to the ics pgnd pin.
ltc3731h 3731hfb func t ional diagra m figure 2 switch logic clk2 clk1 sw shdn b 0.55v 3mv fcb top boost tg c b c in d b pgnd bot bg v cc v cc (vdr) v in + v out 3731h f02 drop out det run soft- start bot force bot s r q q clk3 oscillator pllfltr 50k 0.600v 0.660v 1.5a 6v rst shdn fcb run/ss c ss 5(v fb ) 5(v fb ) 0.86v slope comp + ? sense + v cc 36k 54k 54k 2.4v ss clamp i 1 sgnd 0.600v internal supply v cc c cc v cc phase det pllin duplicate for second and third controller channels +? +? r sense l c out + f in r lp c lp + ? + ? + ? eain v fb r1 ov i th c c r c pgood fcb + ? ? + + 1.2v v ref uv reset v cc eain 0.66v rs latch fcb 0.6v 0.54v protection phasmd clkout + ? i 2 sense ? 36k ea 1.2v uvadj + ? shed r2 100s delay
ltc3731h 0 3731hfb o pera t ion main control loop the ic uses a constant frequency, current mode step-down architecture. during normal operation, each top mosfet is turned on each cycle when the oscillator sets the rs latch, and turned off when the main current comparator, i 1 , resets each rs latch. the peak inductor current at which i 1 resets the rs latch is controlled by the voltage on the i th pin, which is the output of the error amplifier ea. the eain pin receives a portion of output voltage feedback signal through the external resistive divider and is compared to the internal reference voltage. when the load current increases, it causes a slight decrease in the eain pin voltage relative to the 0.6v reference, which in turn causes the i th voltage to increase until each inductors average current matches one third of the new load current (assuming all three current sensing resistors are equal). in burst mode operation and stage shedding mode, after each top mosfet has turned off, the bottom mosfet is turned on until either the inductor current starts to reverse, as indicated by current comparator i 2 , or the beginning of the next cycle. the top mosfet drivers are biased from floating bootstrap capacitor c b , which is normally recharged through an external schottky diode when the top fet is turned off. when v in decreases to a voltage close to v out , however, the loop may enter dropout and attempt to turn on the top mosfet continuously. the dropout detector counts the number of oscillator cycles that the bottom mosfet remains off and periodically forces a brief on period to allow c b to recharge. the main control loop is shut down by pulling the run/ss pin low. releasing run/ss allows an internal 1.5a current source to charge soft-start capacitor c ss . when c ss reaches 1.5v, the main control loop is enabled and the internally buffered i th voltage is clamped but allowed to ramp as the voltage on c ss continues to ramp. this soft-start clamping prevents abrupt current from being drawn from the input power source. when the run/ss pin is low, all functions are kept in a controlled state. the run/ss pin is pulled low when the supply input voltage is below 4v, when the undervoltage lockout pin (uvadj) is below 1.2v, or when the ic die temperature rises above 160c. low current operation the fcb pin is a logic input to select between three modes of operation. a) burst mode operation when the fcb pin voltage is below 0.6v, the controller performs as a continuous, pwm current mode synchro- nous switching regulator. the top and bottom mosfets are alternately turned on to maintain the output voltage independent of direction of inductor current. when the fcb pin is below v cc C 1.5v but greater than 0.6v, the controller performs as a burst mode switching regulator. burst mode operation sets a minimum output current level before turning off the top switch and turns off the synchronous mosfet(s) when the inductor current goes negative. this combination of requirements will, at low current, force the i th pin below a voltage threshold that will temporarily shut off both output mosfets until the output voltage drops slightly. there is a burst compara- tor having 60mv of hysteresis tied to the i th pin. this hysteresis results in output signals to the mosfets that turn them on for several cycles, followed by a variable sleep interval depending upon the load current. the resultant output voltage ripple is held to a very small value by having the hysteretic comparator after the error amplifier gain block. b) stage shedding operation when the fcb pin is tied to the v cc pin, burst mode opera- tion is disabled and the forced minimum inductor current requirement is removed. this provides constant frequency, discontinuous current operation over the widest possible output current range. at approximately 10% of maximum designed load current, the second and third output stages are shut off and the phase 1 controller alone is active in discontinuous current mode. this stage shedding opti- mizes efficiency by eliminating the gate charging losses and switching losses of the other two output stages. additional cycles will be skipped when the output load current drops below 1% of maximum designed load current in order to maintain the output voltage. this stage shedding operation is not as efficient as burst mode operation at very light loads, but does provide lower noise, constant frequency operating mode down to very light load conditions. (refer to functional diagram)
ltc3731h 3731hfb c) continuous current operation tying the fcb pin to ground will force continuous current operation. this is the least efficient operating mode, but may be desirable in certain applications. the output can source or sink current in this mode. when sinking current while in forced continuous operation, the controller will cause current to flow back into the input filter capacitor. if large enough, the input capacitor will prevent the input supply from boosting to unacceptably high levels; see c in /c out selection in the applications information section. frequency synchronization the phase-locked loop allows the internal oscillator to be synchronized to an external source using the pllin pin. the output of the phase detector at the pllfltr pin is also the dc frequency control input of the oscillator, which operates over a 225khz to 680khz range corresponding to a voltage input from 0v to 2.4v. when locked, the pll aligns the turn on of the top mosfet to the rising edge of the synchronizing signal. when no frequency information is supplied to the pllin pin, pllfltr goes low, forcing the oscillator to minimum frequency. a dc source can be applied to the pllfltr pin to externally set the desired operating frequency. a discharge current of approximately 20a will be present at the pin with no pllin input signal. input capacitance esr requirements and efficiency losses are reduced substantially in a multiphase architecture because the peak current drawn from the input capacitor is effectively divided by the number of phases used and power loss is proportional to the rms current squared. a 3-stage, single output voltage implementation can reduce input path power loss by 90%. power good the pgood pin is connected to the drain of an internal n - c h annel mosfet. the mosfet is turned on once an internal delay of about 100s has elapsed and the output voltage has been away from its nominal value by greater than 10%. if the output returns to normal prior to the delay timeout, the timer is reset. there is no delay time for the rising of the pgood output once the output voltage is within the 10% window. phase mode the phasmd pin determines the phase shift between the rising edge of the tg1 output and the rising edge of the clkout signal. grounding the pin will result in 30 degrees phase shift and tying the pin to v cc will result in 60 degrees. these phase shift values enable extension to 6- and 12-phase systems. the pgood function above and the phasmd function are tied to a common pin in the uh package. undervoltage shutdown adjust the voltage applied to the uvadj pin is compared to the internal 1.2v reference to have an externally programmable undervoltage shutdown. the run/ss pin is internally held low until the voltage applied to the uvadj pin exceeds the 1.2v threshold. short-circuit detection the run/ss capacitor is used initially to turn on and limit the inrush current from the input power source. once the controllers have been given time, as determined by the capacitor on the run/ss pin, to charge up the output capacitors and provide full load current, the run/ss capacitor is then used as a short-circuit timeout circuit. if the output voltage falls to less than 70% of its nominal output voltage, the run/ss capacitor begins discharg- ing, assuming that the output is in a severe overcurrent and/or short-circuit condition. if the condition lasts for a long enough period, as determined by the size of the run/ss capacitor, the controller will be shut down until the run/ss pin voltage is recycled. this built-in latchoff can be overridden by providing >5a at a compliance of 3.8v to the run/ss pin. this additional current shortens the soft-start period but prevents net discharge of the run/ss capacitor during a severe overcurrent and/or short-circuit condition. foldback current limiting is activated when the output voltage falls below 70% of its nominal level whether or not the short-circuit latchoff circuit is enabled. foldback current limit can be overridden by clamping the eain pin such that the voltage is held above the (70%)(0.6v) or 0.42v level even when the actual output voltage is low. up to 100a of input current can safely be accommodated by the run/ss pin. o pera t ion (refer to functional diagram)
ltc3731h 3731hfb o pera t ion (refer to functional diagram) input undervoltage reset the run/ss capacitor will be reset if the input voltage (v cc ) is allowed to fall below approximately 4v. the capacitor on the run/ss pin will be discharged until the short-circuit arming latch is disarmed. the run/ss capacitor will attempt to cycle through a normal soft-start ramp up after the v cc supply rises above 4v. this circuit prevents power supply latchoff in the event of input power switching break-before-make situations. the pgood pin is held low during start-up until the run/ss capacitor rises above the short-circuit latchoff arming threshold of approximately 3.8v. a pplica t ions i n f or m a t ion the basic application circuit is shown in figure 1 on the first page of this data sheet. external component selection is driven by the load requirement, and normally begins with the selection of an inductance value based upon the desired operating frequency, inductor current and output voltage ripple requirements. once the inductors and op- erating frequency have been chosen, the current sensing resistors can be calculated. next, the power mosfets and schottky diodes are selected. finally, c in and c out are selected according to the voltage ripple require- ments. the circuit shown in figure 1 can be configured for operation up to a mosfet supply voltage of 28v (limited by the external mosfets and possibly the mini- mum on-time). operating frequency the ic uses a constant frequency, phase-lockable ar- chitecture with the frequency determined by an internal capacitor. this capacitor is charged by a fixed current plus an additional current which is proportional to the voltage applied to the pllfltr pin. refer to the phase-locked loop and frequency synchronization section for additional information. a graph for the voltage applied to the pllfltr pin versus frequency is given in figure 3. as the operating frequency is increased the gate charge losses will be higher, reducing efficiency (see efficiency considerations). the maximum switching frequency is approximately 680khz. inductor value calculation and output ripple current the operating frequency and inductor selection are inter- related in that higher operating frequencies allow the use of smaller inductor and capacitor values. so why would anyone ever choose to operate at lower frequencies with larger components? the answer is efficiency. a higher frequency generally results in lower efficiency because of mosfet gate charge and transition losses. in addi- tion to this basic tradeoff, the effect of inductor value on ripple current and low current operation must also be considered. the polyphase approach reduces both input and output ripple currents while optimizing individual output stages to run at a lower fundamental frequency, enhancing efficiency. the inductor value has a direct effect on ripple current. the inductor ripple current ?i l per individual section, n, decreases with higher inductance or frequency and increases with higher v in or v out : ?i v fl v v l out out in = ? ? ? ? ? ? ? 1 where f is the individual output stage operating frequency. figure 3. operating frequency vs v pllfltr pllfltr pin voltage (v) 0 operating frequency (khz) 3731h f03 700 600 500 400 300 200 0.5 1 1.5 2 2.5
ltc3731h 3731hfb a pplica t ions i n f or m a t ion in a polyphase converter, the net ripple current seen by the output capacitor is much smaller than the individual inductor ripple currents due to the ripple cancellation. the details on how to calculate the net output ripple current can be found in application note 77. figure 4 shows the net ripple current seen by the output capacitors for the different phase configurations. the output ripple current is plotted for a fixed output voltage as the duty factor is varied between 10% and 90% on the x - axis. the output ripple current is normalized against the inductor ripple current at zero duty factor. the graph can be used in place of tedious calculations. as shown in figure 4, the zero output ripple current is obtained when: v v k n where k n out in = = 1 2 1, , ..., ? so the number of phases used can be selected to minimize the output ripple current and therefore the output ripple voltage at the given input and output voltages. in appli- cations having a highly varying input voltage, additional phases will produce the best results. accepting larger values of ?i l allows the use of low in- ductances but can result in higher output voltage ripple. a reasonable starting point for setting ripple current is ?i l = 0.4(i out )/n, where n is the number of channels and i out is the total load current. remember, the maximum ?i l occurs at the maximum input voltage. the individual inductor ripple currents are constant determined by the input and output voltages, and the inductance. inductor core selection once the value for l1 to l3 is determined, the type of induc- tor must be selected. high efficiency converters generally cannot afford the core loss found in low cost powdered iron cores, forcing the use of ferrite, molypermalloy or kool m cores. actual core loss is independent of core size for a fixed inductor value, but it is very dependent on inductance selected. as inductance increases, core losses go down. unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. ferrite designs have very low core loss and are preferred at high switching frequencies, so design goals cancon- centrate on copper loss and preventing saturation. ferrite core material saturates hard, which means that induc- tance collapses abruptly when the peak design current is exceeded. this results in an abrupt increase in inductor ripple current and consequent output voltage ripple. do not allow the core to saturate! molypermalloy (from magnetics, inc.) is a very good, low loss core material for toroids, but it is more expensive than ferrite. a reasonable compromise from the same manufacturer is kool m. toroids are very space effi- cient, especially when you can use several layers of wire. because they lack a bobbin, mounting is more difficult. however, designs for surface mount are available which do not increase the height significantly. power mosfet and d1, d2, d3 selection at least two external power mosfets must be selected for each of the three output sections: one n-channel mosfet for the top (main) switch and one or more n-channel mosfet(s) for the bottom (synchronous) switch. the number, type and on-resistance of all mosfets selected take into account the voltage step-down ratio as well as the actual position (main or synchronous) in which the mosfet will be used. a much smaller and much lower input capacitance mosfet should be used for the top figure 4. normalized peak output current vs duty factor [i rms = 0.3(i o(p-p) ] duty factor (v out /v in ) 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 3731h f04 6-phase 12-phase 4-phase 3-phase 2-phase 1-phase ?i o(p-p) v o /fl
ltc3731h 3731hfb mosfet in applications that have an output voltage that is less than 1/3 of the input voltage. in applications where v in >> v out , the top mosfets on-resistance is normally less important for overall efficiency than its input capaci- tance at operating frequencies above 300khz. mosfet manufacturers have designed special purpose devices that provide reasonably low on-resistance with significantly reduced input capacitance for the main switch application in switching regulators. the peak-to-peak mosfet gate drive levels are set by the voltage, v cc , requiring the use of logic-level threshold mosfets in most applications. pay close attention to the bv dss specification for the mosfets as well; many of the logic-level mosfets are limited to 30v or less. selection criteria for the power mosfets include the on - resistance r ds(on) , input capacitance, input voltage and maximum output current. mosfet input capacitance is a combination of sev- eral components but can be taken from the typical gate charge curve included on most data sheets (figure 5). the curve is generated by forcing a constant input cur- rent into the gate of a common source, current source loaded stage and then plotting the gate voltage versus time. the initial slope is the effect of the gate-to-source and the gate-to-drain capacitance. the flat portion of the curve is the result of the miller multiplication effect of the drain-to-gate capacitance as the drain drops the voltage across the current source load. the upper sloping line is due to the drain-to-gate accumulation capacitance and the gate-to-source capacitance. the miller charge (the increase in coulombs on the horizontal axis from a to b while the curve is flat) is specified for a given v ds drain a pplica t ions i n f or m a t ion voltage, but can be adjusted for different v ds voltages by multiplying by the ratio of the application v ds to the curve specified v ds values. a way to estimate the c miller term is to take the change in gate charge from points a and b on a manufacturers data sheet and divide by the stated v ds voltage specified. c miller is the most important se- lection criteria for determining the transition loss term in the top mosfet but is not directly specified on mosfet data sheets. c rss and c os are specified sometimes but definitions of these parameters are not included. when the controller is operating in continuous mode the duty cycles for the top and bottom mosfets are given by: main switch duty cycle v v synchronous switch duty cycle v v v out in in out in = = ? ? ? ? ? ? ? the power dissipation for the main and synchronous mosfets at maximum output current are given by: p v v i n r v i n r c v v v f p v v v i n r main out in max ds on in max dr miller cc th il th il sync in out in max ds on = ? ? ? ? ? ? + ( ) + ( )( ) + ? ? ? ? ? ? ( ) = ? ? ? ? ? ? + ( ) 2 2 2 1 2 1 1 1 d d ( ) ( ) ( ) ( ) ? ? ? where n is the number of output stages, d is the tem- perature dependency of r ds(on) , r dr is the effective top driver resistance (approximately 2 at v gs = v miller ), v in is the drain potential and the change in drain potential in the particular application. v th(il) is the data sheet speci- fied typical gate threshold voltage specified in the power mosfet data sheet at the specified drain current. c miller is the calculated capacitance using the gate charge curve from the mosfet data sheet and the technique described above. figure 5. gate charge characteristic + ? v ds v in 3731h f05 v gs miller effect q in a b c miller = (q b ? q a )/v ds v gs v + ?
ltc3731h 3731hfb a pplica t ions i n f or m a t ion both mosfets have i 2 r losses while the topside n - channel equation includes an additional term for transition losses, which peak at the highest input voltage. for v in < 12v, the high current efficiency generally improves with larger mosfets, while for v in > 12v, the transition losses rapidly increase to the point that the use of a higher r ds(on) device with lower c miller actually provides higher efficiency. the synchronous mosfet losses are greatest at high input voltage when the top switch duty factor is low or during a short circuit when the synchronous switch is on close to 100% of the period. the term (1 + d ) is generally given for a mosfet in the form of a normalized r ds(on) vs temperature curve, but d = 0.005/c can be used as an approximation for low voltage mosfets. the schottky diodes (d1 to d3 in figure 1) conduct during the dead time between the conduction of the two large power mosfets. this prevents the body diode of the bot- tom mosfet from turning on, storing charge during the dead time and requiring a reverse recovery period which could cost as much as several percent in efficiency. a 2a to 8a schottky is generally a good compromise for both regions of operation due to the relatively small average current. larger diodes result in additional transition loss due to their larger junction capacitance. c in and c out selection in continuous mode, the source current of each top n - channel mosfet is a square wave of duty cycle v out / v in . a low esr input capacitor sized for the maximum rms current must be used. the details of a close form equation can be found in application note 77. figure 6 shows the input capacitor ripple current for different phase configurations with the output voltage fixed and input volt- age varied. the input ripple current is normalized against the dc output current. the graph can be used in place of tedious calculations. the minimum input ripple current can be achieved when the product of phase number and output voltage, n(v out ), is approximately equal to the input voltage v in or: v v k n where k n out in = = 1 2 1, , ..., ? so the phase number can be chosen to minimize the input capacitor size for the given input and output voltages. in the graph of figure 4, the local maximum input rms capacitor currents are reached when: v v k n where k n out in = = 2 1 1 2 ? , , ..., these worst-case conditions are commonly used for design because even significant deviations do not offer much relief. note that capacitor manufacturers ripple current ratings are often based on only 2000 hours of life. this makes it advisable to further derate the capacitor or to choose a capacitor rated at a higher temperature than required. several capacitors may also be paralleled to meet size or height requirements in the design. always consult the capacitor manufacturer if there is any question. the figure 6 graph shows that the peak rms input current is reduced linearly, inversely proportional to the number n of stages used. it is important to note that the efficiency loss is proportional to the input rms current squared and therefore a 3-stage implementation results in 90% less power loss when compared to a single phase design. bat- tery/input protection fuse resistance (if used), pc board trace and connector resistance losses are also reduced by the reduction of the input ripple current in a polyphase system. the required amount of input capacitance is further duty factor (v out /v in ) 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 0.6 0.5 0.4 0.3 0.2 0.1 0 3731h f06 rms input ripple current dc load current 6-phase 4-phase 12-phase 3-phase 2-phase 1-phase figure 6. normalized input rms ripple current vs duty factor for one to six output stages
ltc3731h 3731hfb reduced by the factor, n, due to the effective increase in the frequency of the current pulses. ceramic capacitors are becoming very popular for small designs but several cautions should be observed. x7r, x5r and y5v are examples of a few of the ceramic materials used as the dielectric layer, and these different dielectrics have very different effect on the capacitance value due to the voltage and temperature conditions ap- plied. physically, if the capacitance value changes due to applied voltage change, there is a concommitant piezo effect which results in radiating sound! a load that draws varying current at an audible rate may cause an attendant varying input voltage on a ceramic capacitor, resulting in an audible signal. a secondary issue relates to the energy flowing back into a ceramic capacitor whose capacitance value is being reduced by the increasing charge. the volt- age can increase at a considerably higher rate than the constant current being supplied because the capacitance value is decreasing as the voltage is increasing! never- theless, ceramic capacitors, when properly selected and used, can provide the lowest overall loss due to their extremely low esr. the selection of c out is driven by the required effective series resistance (esr). typically once the esr requirement is satisfied the capacitance is adequate for filtering. the steady-state output ripple (?v out ) is determined by: ? ? v i esr nfc out ripple out + ? ? ? ? ? ? 1 8 where f = operating frequency of each stage, n is the number of output stages, c out = output capacitance and ?i l = ripple current in each inductor. the output ripple is highest at maximum input voltage since ?i l increases with a pplica t ions i n f or m a t ion input voltage. the output ripple will be less than 50mv at max v in with ?i l = 0.4i out(max) assuming: c out required esr < n ? r sense and c out > 1/(8nf)(r sense ) the emergence of very low esr capacitors in small, surface mount packages makes very small physical implementa- tions possible. the ability to externally compensate the switching regulator loop using the i th pin allows a much wider selection of output capacitor types. the impedance characteristics of each capacitor type is significantly differ- ent than an ideal capacitor and therefore requires accurate modeling or bench evaluation during design. manufacturers such as nichicon, nippon chemi-con and sanyo should be considered for high performance through- hole capacitors. the os-con semiconductor dielectric capacitor available from sanyo and the panasonic sp surface mount types have a good (esr)(size) product. once the esr requirement for c out has been met, the rms current rating generally far exceeds the i ripple(p-p) requirement. ceramic capacitors from avx, taiyo yuden, murata and tokin offer high capacitance value and very low esr, especially applicable for low output voltage applications. in surface mount applications, multiple capacitors may have to be paralleled to meet the esr or rms current handling requirements of the application. aluminum electrolytic and dry tantalum capacitors are both available in surface mount configurations. new special polymer surface mount capacitors offer very low esr also but have much lower capacitive density per unit volume. in the case of tantalum, it is critical that the capacitors are surge tested for use in switching power supplies. several excellent choices are the avx tps, avx tpsv, the kemet t510 series of surface-mount tantalums or the panasonic sp series of surface mount special polymer capacitors
ltc3731h 3731hfb a pplica t ions i n f or m a t ion available in case heights ranging from 2mm to 4mm. other capacitor types include sanyo pos-cap, sanyo os-con, nichicon pl series and sprague 595d series. consult the manufacturer for other specific recommendations. r sense selection for output current once the frequency and inductor have been chosen, r sense1 , r sense2 , r sense3 are determined based on the required peak inductor current. the current comparator has a typical maximum threshold of 75mv/r sense and an input common mode range of sgnd to (1.1) ? v cc . the current comparator threshold sets the peak inductor current, yielding a maximum average output current i max equal to the peak value less half the peak-to-peak ripple current, ?i l . allowing a margin for variations in the ic and external component values yields: r n mv i sense max = 50 the ic works well with values of r sense from 0.002 to 0.02. v cc decoupling the v cc and v dr pins supply power to the internal cir- cuits of the controller and to the top and bottom gate drivers. therefore, they must be bypassed very carefully to ground with ceramic capacitors, type x7r or x5r (de- pending upon the operating temperature environment) of at least 1f immediately next to the ic and preferably an additional 10f placed very close to the ic due to the extremely high instantaneous currents involved. the total capacitance, taking into account the voltage coefficient of ceramic capacitors, should be 100 times as large as the total combined gate charge capacitance of all of the mosfets being driven. good bypassing close to the ic is necessary to supply the high transient currents required by the mosfet gate drivers while keeping the 5v supply quiet enough so as not to disturb the very small-signal high bandwidth of the current comparators. topside mosfet driver supply (c b , d b ) external bootstrap capacitors, c b , connected to the boost pins, supply the gate drive voltages for the top- side mosfets. capacitor c b in the functional diagram is charged though diode d b from v cc when the sw pin is low. when one of the topside mosfets turns on, the driver places the c b voltage across the gate-source of the desired mosfet. this enhances the mosfet and turns on the topside switch. the switch node voltage, sw, rises to v in and the boost pin follows. with the topside mosfet on, the boost voltage is above the input supply (v boost = v cc + v in ). the value of the boost capacitor c b needs to be 30 to 100 times that of the total gate charge capacitance of the topside mosfet(s) as specified on the manufacturers data sheet. the reverse breakdown of d b must be greater than v in(max) . the output voltage is set by an external resistive divider according to the following formula: v v r r out = + ? ? ? ? ? ? 0 6 1 1 2 . the resistive divider is connected to the output as shown in figure 2. soft-start/run function the run/ss pin provides three functions: 1) on/off, 2) soft-start and 3) a defeatable short-circuit latch off timer. soft-start reduces the input power sources surge currents by gradually increasing the controllers current limit (pro- portional to an internal buffered and clamped v ith ). the latchoff timer prevents very short, extreme load transients from tripping the overcurrent latch. a small pull-up cur- rent (>5a) supplied to the run/ss pin will prevent the overcurrent latch from operating. a maximum pull-up cur- rent of 200a is allowed into the run/ss pin even though the voltage at the pin may exceed the absolute maximum rating for the pin. this is a result of the limited current and the internal protection circuit on the pin. the following explanation describes how this function operates.
ltc3731h 3731hfb a pplica t ions i n f or m a t ion an internal 1.5a current source charges up the c ss capacitor. when the voltage on run/ss reaches 1.5v, the controller is permitted to start operating. as the voltage on run/ss increases from 1.5v to 3.5v, the internal current limit is increased from 20mv/r sense to 75mv/r sense . the output current limit ramps up slowly, taking an additional 1s/f to reach full current. the output current thus ramps up slowly, eliminating the starting surge current required from the input power supply. if run/ss has been pulled all the way to ground, there is a delay before starting of approximately: t v a c s f c t v v a c s f c delay ss ss iramp ss ss = = ( ) = ? = ( ) 1 5 1 5 1 3 1 5 1 5 1 . . / . . / by pulling the run/ss controller pin below 0.4v the ic is put into low current shutdown (i q < 100a). the run/ss pin can be driven directly from logic as shown in figure 7. diode, d1, in figure 7 reduces the start delay but allows c ss to ramp up slowly, providing the soft-start function. the run/ss pin has an internal 6v zener clamp (see the functional diagram). fault conditions: overcurrent latchoff the run/ss pins also provide the ability to latch off the controllers when an overcurrent condition is detected. the run/ss capacitor is used initially to turn on and limit the inrush current of all three output stages. after the con- trollers have been started and been given adequate time to charge up the output capacitor and provide full load current, the run/ss capacitor is used for a short-circuit timer. if the output voltage falls to less than 70% of its nominal value, the run/ss capacitor begins discharging on the assumption that the output is in an overcurrent condition. if the condition lasts for a long enough period, as determined by the size of the run/ss capacitor, the discharge current, and the circuit trip point, the controller will be shut down until the run/ss pin voltage is recycled. if the overload occurs during start-up, the time can be approximated by: t lo1 >> (c ss ? 0.6v)/(1.5a) = 4 ? 10 5 (c ss ) if the overload occurs after start-up, the voltage on the run/ss capacitor will continue charging and will provide additional time before latching off: t lo2 >> (c ss ? 3v)/(1.5a) = 2 ? 10 6 (c ss ) this built-in overcurrent latchoff can be overridden by providing a pull-up resistor to the run/ss pin from v cc as shown in figure 7. when v cc is 5v, a 200k resistance will prevent the discharge of the run/ss capacitor dur- ing an overcurrent condition but also shortens the soft- start period, so a larger run/ss capacitor value may be required. why should you defeat overcurrent latchoff? during the prototyping stage of a design, there may be a problem with noise pick-up or poor layout causing the protection circuit to latch off the controller. defeating this feature allows troubleshooting of the circuit and pc layout. the internal foldback current limiting still remains active, thereby pro- tecting the power supply system from failure. a decision can be made after the design is complete whether to rely solely on foldback current limiting or to enable the latchoff feature by removing the pull-up resistor. the value of the soft-start capacitor c ss may need to be scaled with output current, output capacitance and load current characteristics. the minimum soft-start capaci- tance is given by: c ss > (c out )(v out ) (10 C4 ) (r sense ) the minimum recommended soft-start capacitor of c ss = 0.1f will be sufficient for most applications. run/ss pin 3.3v or 5v run/ss pin 5v v cc r ss c ss c ss 3731h f07 d1 shdn shdn figure 7. run/ss pin interfacing
ltc3731h 3731hfb a pplica t ions i n f or m a t ion figure 8. foldback current elimination current foldback in certain applications, it may be desirable to defeat the internal current foldback function. a negative impedance is experienced when powering a switching regulator. that is, the input current is higher at a lower v in and decreases as v in is increased. current foldback is designed to ac- commodate a normal, resistive load having increasing current draw with increasing voltage. the eain pin should be artificially held 70% above its nominal operating level of 0.6v, or 0.42v in order to prevent the ic from folding back the peak current level. a suggested circuit is shown in figure 8. the emitter of q1 will hold up the eain pin to a voltage in the absence of v out that will prevent the internal sensing circuitry from reducing the peak output current. remov- ing the function in this manner eliminates the external mosfets protective feature under short-circuit conditions. this technique will also prevent the short-circuit latchoff function from turning off the part during a short-circuit event and the peak output current will only be limited to n ? 75mv/r sense . undervoltage reset in the event that the input power source to the ic (v cc ) drops below 4v, the run/ss capacitor will be discharged to ground. when v cc rises above 4v, the run/ss capacitor will be allowed to recharge and initiate another soft-start turn-on attempt. this may be useful in applications that switch between two supplies that are not diode connected, but note that this cannot make up for the resultant inter- ruption of the regulated output. phase-locked loop and frequency synchronization the ic has a phase-locked loop comprised of an internal voltage controlled oscillator and phase detector. this allows the top mosfet of output stage 1s turn-on to be locked to the rising edge of an external source. the frequency range of the voltage controlled oscillator is 50% around the center frequency f o . a voltage applied to the pllfltr pin of 1.2v corresponds to a frequency of approximately 400khz. the nominal operating frequency range of the ic is 225khz to 680khz. the phase detector used is an edge sensitive digital type that provides zero degrees phase shift between the external and internal oscillators. this type of phase detector will not lock the internal oscillator to harmonics of the input frequency. the pll hold-in range, ?f h , is equal to the capture range, ?f c : ?f h = ?f c = 0.5 f o the output of the phase detector is a complementary pair of current sources charging or discharging the external filter components on the pllfltr pin. a simplified block diagram is shown in figure 9. if the external frequency (f pllin ) is greater than the os- cillator frequency, f osc , current is sourced continuously, pulling up the pllfltr pin. when the external frequency is less than f osc , current is sunk continuously, pulling down v cc 3731h f08 calculate for 0.42v to 0.55v v cc eain q1 ltc3731h
ltc3731h 0 3731hfb a pplica t ions i n f or m a t ion the pllfltr pin. if the external and internal frequencies are the same, but exhibit a phase difference, the current sources turn on for an amount of time corresponding to the phase difference. thus, the voltage on the pllfltr pin is adjusted until the phase and frequency of the external and internal oscillators are identical. at this stable operat- ing point, the phase comparator output is open and the filter capacitor c lp holds the voltage. the ic pllin pin must be driven from a low impedance source such as a logic gate located close to the pin. when using multiple ics for a phase-locked system, the pllfltr pin of the master oscillator should be biased at a voltage that will guarantee the slave oscillator(s) ability to lock onto the masters frequency. a voltage of 1.7v or below applied to the master oscillators pllfltr pin is recommended in order to meet this requirement. the resultant operating frequency will be approximately 550khz for 1.7v. the loop filter components (c lp , r lp ) smooth out the current pulses from the phase detector and provide a stable input to the voltage controlled oscillator. the filter components c lp and r lp determine how fast the loop acquires lock. typically r lp =10k and c lp ranges from 0.01f to 0.1f. minimum on-time considerations minimum on-time, t on(min) , is the smallest time duration that the ic is capable of turning on the top mosfet. it is determined by internal timing delays and the gate charge of the top mosfet. low duty cycle applications may ap- proach this minimum on-time limit and care should be taken to ensure that: t v v f on min out in ( ) < ( ) if the duty cycle falls below what can be accommodated by the minimum on-time, the ic will begin to skip every other cycle, resulting in half-frequency operation. the output voltage will continue to be regulated, but the ripple current and ripple voltage will increase. the minimum on-time for the ic is generally about 110ns. however, as the peak sense voltage decreases the minimum on-time gradually increases. this is of particular concern in forced continuous applications with low ripple current at light loads. if the duty cycle drops below the minimum on-time limit in this situation, a significant amount of cycle skipping can occur with correspondingly larger current and voltage ripple. if an application can operate close to the minimum on-time limit, an inductor must be chosen that is low enough in value to provide sufficient ripple amplitude to meet the minimum on-time requirement. as a general rule, keep the inductor ripple current for each channel equal to or greater than 30% of i out(max) at v in(max) . figure 9. phase-locked loop block diagram external osc 2.4v r lp 10k c lp osc digital phase/ frequency detector phase detector/ oscillator pllin 3731h f09 pllfltr 50k
ltc3731h 3731hfb a pplica t ions i n f or m a t ion efficiency considerations the percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. percent efficiency can be expressed as: %efficiency = 100% C (l1 + l2 + l3 + ...) where l1, l2, etc. are the individual losses as a percent- age of input power. checking transient response the regulator loop response can be checked by look- ing at the load transient response. switching regulators take several cycles to respond to a step in dc (resistive) load current. when a load step occurs, v out shifts by an amount equal to ?i load ? esr, where esr is the effective series resistance of c out . ?i load also begins to charge or discharge c out , generating the feedback error signal that forces the regulator to adapt to the current change and return v out to its steady-state value. during this recovery time, v out can be monitored for excessive overshoot or ringing, which would indicate a stability problem. the availability of the i th pin not only allows optimization of control loop behavior, but also provides a dc-coupled and ac-filtered closed-loop response test point. the dc step, rise time and settling at this test point truly reflects the closed-loop response. assuming a predominantly second order system, phase margin and/or damping fac- tor can be estimated using the percentage of overshoot seen at this pin. the bandwidth can also be estimated by examining the rise time at the pin. the i th external components shown in the figure 1 circuit will provide an adequate starting point for most applications. the i th series r c -c c filter sets the dominant pole-zero loop compensation. the values can be modified slightly (from 0.2 to 5 times their suggested values) to maximize transient response once the final pc layout is done and the particular output capacitor type and value have been determined. the output capacitors need to be decided upon because the various types and values determine the loop feedback factor gain and phase. an output current pulse of 20% to 80% of full load current having a rise time of <2s will produce output voltage and i th pin waveforms that will give a sense of the overall loop stability without breaking the feedback loop. the initial output voltage step, resulting from the step change in output current, may not be within the bandwidth of the feedback loop, so this signal cannot be used to determine phase margin. this is why it is better to look at the i th pin signal which is in the feedback loop and is the filtered and compensated control loop response. the gain of the loop will be increased by increasing r c and the bandwidth of the loop will be in- creased by decreasing c c . if r c is increased by the same factor that c c . is decreased, the zero frequency will be kept the same, thereby keeping the phase the same in the most critical frequency range of the feedback loop. the output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual overall supply performance. a second, more severe transient is caused by switching in loads with large (>1f) supply bypass capacitors. the discharged bypass capacitors are effectively put in parallel with c out , causing a rapid drop in v out . no regulator can alter its delivery of current quickly enough to prevent this sudden step change in output voltage if the load switch resistance is low and it is driven quickly. if c load is greater than 2% of c out , the switch rise time should be controlled so that the load rise time is limited to approximately 1000 ? r sense ? c load . thus a 250f capacitor and a 2m r sense resistor would require a 500s rise time, limiting the charging current to about 1a.
ltc3731h 3731hfb a pplica t ions i n f or m a t ion automotive considerations: plugging into the cigarette lighter as battery-powered devices go mobile, there is a natural interest in plugging into the cigarette lighter in order to conserve or even recharge battery packs during operation. but before you connect, be advised: you are plugging into the supply from hell. the main battery line in an automobile is the source of a number of nasty potential transients, in- cluding load dump, reverse battery and double battery. load dump is the result of a loose battery cable. when the cable breaks connection, the field collapse in the alterna- tor can cause a positive spike as high as 60v which takes several hundred milliseconds to decay. reverse battery is just what it says, while double battery is a consequence of tow-truck operators finding that a 24v jump start cranks cold engines faster than 12v. the network shown in figure 10 is the most straightforward approach to protect a dc/dc converter from the ravages of an automotive battery line. the series diode prevents current from flowing during reverse battery, while the transient suppressor clamps the input voltage during load dump. note that the transient suppressor should not conduct during double-battery operation, but must still clamp the input voltage below breakdown of the converter. although the ic has a maximum input voltage of 32v on the sw pins, most applications will be limited to 30v by the mosfet bv dss . design example as a design example, assume v cc = 5v, v in = 12v(nominal), v in = 20v(max), v out = 1.3v, i max = 45a and f = 400khz. the inductance value is chosen first based upon a 30% ripple current assumption. the highest value of ripple current in each output stage occurs at the maximum input voltage. l v f i v v v khz out out in = ? ( ) ? ? ? ? ? ? ? = ( )( 1 1 3 400 30 . % ))( ) ? ? ? ? ? ? ? 15 1 1 3 20 0 68 a v v h . . using l = 0.6h, a commonly available value results in 34% ripple current. the worst-case output ripple for the three stages operating in parallel will be less than 11% of the peak output current. r sense1 , r sense2 and r sense3 can be calculated by using a conservative maximum sense current threshold of 65mv and taking into account half of the ripple current: r mv a sense = + ? ? ? ? ? ? = ? 65 15 1 34 2 0 0037 % . use a commonly available 0.003 sense resistor. next verify the minimum on-time is not violated. the minimum on-time occurs at maximum v cc : t v v f v v khz ns on min out in max ( ) = ( ) = ( ) = ( ) .1 3 20 400 162 the output voltage will be set by the resistive divider from the diffout pin to sgnd, r1 and r2 in the functional diagram. set r1 = 13.3k and r2 = 11.3k. figure 10. automotive application protection + ltc3731h v cc 5v v bat 12v 3731h f10
ltc3731h 3731hfb a pplica t ions i n f or m a t ion the power dissipation on the topside mosfet can be estimated. using a fairchild fds6688 for example, r ds(on) = 7m, c miller = 15nc/15v = 1000pf. at maximum input voltage with t(estimated) = 50c: p v v c c a pf v v v khz w main ( ) + ( ) ? ( ) [ ] + ( ) ( )( ) ? ? ? ? ? ? ? ( )( ) + ? ? ? ? ? ? ( ) = 1 8 20 15 1 0 005 50 25 0 007 20 45 2 3 2 1000 1 5 1 8 1 1 8 400 2 2 2 2 . . . ? . . . ? the worst-case power dissipation by the synchronous mosfet under normal operating conditions at elevated ambient temperature and estimated 50c junction tem- perature rise is: p v v v a w sync = ? ( ) ( ) ? ( ) = 20 1 3 20 15 1 25 0 007 1 84 2 . . . . a short circuit to ground will result in a folded back current of: i mv m ns v h a sc + ( ) ? + ( ) ? ? ? ? ? ? = 25 2 3 1 2 150 20 0 6 7 5 . . with a typical value of r ds(on) and d = (0.005/c)(50c) = 0.25. the resulting power dissipated in the bottom mosfet is: p sync = (7.5a) 2 (1.25)(0.007) 0.5w which is less than one third of the normal, full load con- ditions. incidentally, since the load no longer dissipates any power, total system power is decreased by over 90%. therefore, the system actually cools significantly during a shorted condition! pc board layout checklist when laying out the printed circuit board, the following checklist should be used to ensure proper operation of the ic. these items are also illustrated graphically in the layout diagram of figure 11. check the following in the pc layout: 1) are the signal and power ground paths isolated? keep the sgnd at one end of a printed circuit path thus prevent- ing mosfet currents from traveling under the ic. the ic signal ground pin should be used to hook up all control circuitry on one side of the ic, routing the copper through sgnd, under the ic covering the shadow of the package, connecting to the pgnd pin and then continuing on to the (C) plates of c in and c out . the v cc decoupling capacitor should be placed immediately adjacent to the ic between the v cc pin and pgnd. a 1f ceramic capacitor of the x7r or x5r type is small enough to fit very close to the ic to minimize the ill effects of the large current pulses drawn to drive the bottom mosfets. an additional 5f to 10f of ceramic, tantalum or other very low esr capacitance is recommended in order to keep the internal ic supply quiet. the power ground returns to the sources of the bottom n - channel mosfets, anodes of the schottky diodes and (C) plates of c in , which should have as short lead lengths as possible. 2) does the v fb pin connect directly to the feedback re- sistors? the resistive divider r1/r2 must be connected between the (+) plate of c out and signal ground. 3) are the sense C and sense + printed circuit traces for each channel routed together with minimum pc trace spac- ing? the filter capacitors between sense + and sense C for each channel should be as close as possible to the pins of the ic. connect the sense C and sense + pins to the pads of the sense resistor as illustrated in figure 12. 4) do the (+) plates of c pwr connect to the drains of the topside mosfets as closely as possible? this capacitor provides the pulsed current to the mosfets. 5) keep the switching nodes, switch, boost and tg away from sensitive small-signal nodes (sense + , sense C , eain). ideally the switch, boost and tg printed circuit traces should be routed away and separated from the ic and especially the quiet side of the ic. separate the high dv/dt traces from sensitive small-signal nodes with ground traces or ground planes. 6) use a low impedance source such as a logic gate to drive the pllin pin and keep the lead as short as possible.
ltc3731h 3731hfb 7) the 47pf to 330pf ceramic capacitor between the i th pin and signal ground should be placed as close as pos- sible to the ic. figure 11 illustrates all branch currents in a three-phase switching regulator. it becomes very clear after study- ing the current waveforms why it is critical to keep the high switching current paths to a small physical size. high electric and magnetic fields will radiate from these loops just as radio stations transmit signals. the output capacitor ground should return to the negative terminal a pplica t ions i n f or m a t ion + r in v in v out c in bold lines indicate high, switching currents. keep lines to a minimum length. + c out d3 d2 sw2 d1 l1 sw1 r sense1 l2 r sense2 l3 sw3 r sense3 3731h f11 r l sense + ltc3731h 1000pf inductor output capacitor sense resistor 3731h f12 sense ? figure 11. branch current waveforms figure 12. kelvin sensing r sense
ltc3731h 3731hfb a pplica t ions i n f or m a t ion of the input capacitor and not share a common ground path with any switched current paths. the left half of the circuit gives rise to the noise generated by a switching regulator. the ground terminations of the synchronous mosfets and schottky diodes should return to the bot- tom plate(s) of the input capacitor(s) with a short isolated pc trace since very high switched currents are present. a separate isolated path from the bottom plate(s) of the input and output capacitor(s) should be used to tie in the ic power ground pin (pgnd). this technique keeps inherent signals generated by high current pulses taking alternate current paths that have finite impedances during the total period of the switching regulator. external opti-loop compensation allows overcompensation for pc layouts which are not optimized but this is not the recommended design procedure. simplified visual explanation of how a 3-phase controller reduces both input and output rms ripple current the effect of multiphase power supply design significantly reduces the amount of ripple current in both the input and output capacitors. the rms input ripple current is divided by, and the effective ripple frequency is multiplied up by the number of phases used (assuming that the input volt- age is greater than the number of phases used times the output voltage). the output ripple amplitude is also reduced by, and the effective ripple frequency is increased by the number of phases used. figure 13 graphically illustrates the principle. v sw single phase triple phase i cin i cout v sw1 v sw2 v sw3 i l1 i l2 i l3 i cin i cout 3731h f13 figure 13. single and polyphase current waveforms
ltc3731h 3731hfb a pplica t ions i n f or m a t ion the worst-case input rms ripple current for a single stage design peaks at twice the value of the output voltage. the worst-case input rms ripple current for a two stage design results in peaks at 1/4 and 3/4 of the input voltage, and the worst-case input rms ripple current for a three stage design results in peaks at 1/6, 1/2, and 5/6 of the input voltage. the peaks, however, are at ever decreasing levels with the addition of more phases. a higher effective duty factor results because the duty factors add as long as the currents in each stage are balanced. refer to an19 for a detailed description of how to calculate rms current for the single stage switching regulator. figure 6 illustrates the rms input current drawn from the input capacitance versus the duty cycle as determined by the ratio of input and output voltage. the peak input rms current level of the single phase system is reduced by 2/3 in a 3-phase solution due to the current splitting between the three stages. the output ripple current is reduced significantly when compared to the single phase solution using the same inductance value because the v out /l discharge currents term from the stages that has their bottom mosfets on subtract current from the (v cc C v out )/l charging current resulting from the stage which has its top mosfet on. the output ripple current for a 3-phase design is: i p-p = ( )( ) ( ) > v f l dc v v out in out 1 3 3 ? the ripple frequency is also increased by three, further re- ducing the required output capacitance when v cc < 3v out as illustrated in figure 6. the addition of more phases, by phase locking addi- tional controllers, always results in no net input or output ripple at v out /v in ratios equal to the number of stages implemented. designing a system with multiple stages close to the v out /v in ratio will significantly reduce the ripple voltage at the input and outputs and thereby improve efficiency, physical size and heat generation of the overall switching power supply. refer to application note 77 for more information on polyphase circuits. efficiency calculation to estimate efficiency, the dc loss terms include the input and output capacitor esr, each mosfet r ds(on) , inductor resistance r l , the sense resistance r sense and the forward drop of the schottky rectifier at the operating output current and temperature. typical values for the design example given previously in this data sheet are: main mosfet r ds(on) = 7m (9m at 90c) sync mosfet r ds(on) = 7m (9m at 90c) c inesr = 20m c outesr = 3m r l = 2.5m r sense = 3m v schottky = 0.8v at 15a (0.7v at 90c) v out = 1.3v v in = 12v i max = 45a d = 0.5%c (mosfet temperature coefficient) n = 3 f = 400khz the main mosfet is on for the duty factor v out /v in and the synchronous mosfet is on for the rest of the period or simply (1 C v out /v in ). assuming the ripple current is small, the ac loss in the inductor can be made small if a good quality inductor is chosen. the average current, i out , is used to simplify the calculations. the equation below is not exact but should provide a good technique for the comparison of selected components and give a result that is within 10% to 20% of the final application. determining the mosfets die temperature may require iterative calculations if one is not familiar with typical performance. a maximum operating junction temperature of 90 to 100c for the mosfets is recommended for high reliability applications. common output path dc loss: p n i n r r c lo compath max l sense outesr ? ? ? ? ? ? + ( ) + 2 sss this totals 3.7w + c outesr loss.
ltc3731h 3731hfb a pplica t ions i n f or m a t ion total of all three main mosfets dc loss: p n v v i n r main out in max ds on = ? ? ? ? ? ? ? ? ? ? ? ? + ( ) 2 1 d ( )) + c loss inesr this totals 0.87w + c inesr loss (at 90c). total of all three synchronous mosfets dc loss: p n v v i n r sync out in max ds = ? ? ? ? ? ? ? ? ? ? ? ? + ( ) 1 1 2 ? ( d oon) this totals 7.2w at 90c. total of all three main mosfets ac loss: p v a pf v v v khz w main in ? + ? ? ? ? ? ? = 3 45 2 3 2 1000 1 5 1 8 1 1 8 400 6 3 2 ( ) ( )( ) ( )( ) ? . . ( ) . this totals 1w at v in = 8v, 2.25w at v in = 12v and 6.25w at v in = 20v. total of all three synchronous mosfets ac gate loss: ( ) ( ) ( )( ) ( ) 3 6 15 4 5 q v v f nc v v e g in dsspec in dsspec = this totals 0.08w at v in = 8v, 0.12w at v in = 12v and 0.19w at v in = 20v. the bottom mosfet does not experience the miller capacitance dissipation issue that the main switch does because the bottom switch turns on when its drain is close to ground. the schottky rectifier loss assuming 50ns nonoverlap time: 2 ? 3(0.7v)(15a)(50ns)(4e5) this totals 1.26w. the total output power is (1.3v)(45a) = 58.5w and the total input power is approximately 60w so the % loss of each component is as follows: main switch s ac loss (v in = 12v) 2.25w 3.75% main switchs dc loss 0.87w 1.5% synchronous switch ac loss 0.19w 0.3% synchronous switch dc loss 7.2w 12% power path loss 3.7w 6.1% the numbers above represent the values at v in = 12v. it can be seen from this simple example that two things can be done to improve efficiency: 1) use two mosfets on the synchronous side and 2) use a smaller mosfet for the main switch with smaller c miller to better balance the ac loss with the dc loss. a smaller, less expensive mosfet can actually perform better in the task of the main switch.
ltc3731h 3731hfb typical a pplica t ions figure 14. 3-phase 65a power supply 0.01f 1f 10k v cc sync in 300khz 300pf 1000pf s1 + s1 ? s2 + s2 ? s3 ? s3 + v cc pllin pllfltr fcb nc nc nc ltc3731hg eain sgnd sense1 + sense1 ? sense2 + sense2 ? sense3 ? sense3 + run/ss i th i th uvadj clk 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 pgood boost1 tg1 sw1 boost2 tg2 sw2 v dr bg1 pgnd bg2 bg3 sw3 tg3 boost3 phasmd sgnd 1000pf optional filter for synchronization 100pf 6.04k 9.09k 10 v5 5v to 7v v in m1 m2 d1 s1 + s1 ? l1 0.002 0.01f 2.2k 3.3nf 330pf 1000pf 1f nc 3731h f14 v in : 3.3v to 20v v out : 1.5v at 65a switching frequency: 300khz pgood 47k 1 1000pf 10f 0.1f v5 0.1f 0.1f v5 v5 v in m3 m4 d2 s2 + s2 ? l2 0.002 v in m5 m6 d3 s3 + s3 ? l3 0.002 10f 6.3v s3 c out v in 3.3v to 20v v out 1.5v at 65a + 10f 25v s5 c in 68f 25v + c in : sanyo os-con 25sp68m c out : 270f/2v s8 panasonic sp eeue0d271r or 470f/2.5v s6 sanyo poscap 2r5 tpd470m d1 to d3: diodes inc. b340a l1 to l3: 0.8h sumida cep125-0r8 m1, m3, m5: irf7821w s2, si7860dp or hat2168 s2 m2, m4, m6: irf7832 s2, si7892dp s2 or hat2165 s2 v in 18k 12k
ltc3731h 3731hfb typical a pplica t ions 2.5v/100a power supply 3.3k v cc 220pf eain 1000pf s1 + s1 ? s2 + s2 ? s3 ? s3 + v cc pllin pllfltr fcb nc nc nc ltc3731hg eain sgnd sense1 + sense1 ? sense2 + sense2 ? sense3 ? sense3 + run/ss i th uvadj clkout 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 pgood boost1 tg1 sw1 boost2 tg2 sw2 v dr bg1 pgnd bg2 bg3 sw3 tg3 boost3 phasmd sgnd2 4.64k 14.7k 330pf 8.2k 1k v in m1 x2 m2,3 d1 s1 + s1 ? l1 0.002 eain run/ss run/ss 0.1f 1000pf clk1 pgood boost1 10k 10 1 1000pf 0.1f 0.1f 0.1f boost2 boost3 10f cer. v in m4 x2 m5,6 d2 s2 + s2 ? l2 0.002 v in m7 x2 m8,9 d3 s3 + s3 ? l3 0.002 c out v in v out v cc v cc sync in v cc v5 + c in + 3731h f15 notes: v5: 5v to 7v v in : 10v to 14v; v out : 2.5v/100a switching frequency: 500khz (v5 = 5v) m1, m4, m7, m10, m13, m16: siliconix si7390dp or hat2168 m2, m3, m5, m6, m8, m9, m11, m12, m14, m15, m17, m18: siliconix si7356dp or hat2165 d1 to d6: b320a l1 to l6: toko fdh1040: 0.56h c in : 10f/16v ceramic s10 + 270f/16v sanyo os-con c out : 100f/6.3v/x5r s10 + 330f/4v s8 v in 357k 121k 10s6 10s6 1000pf 68pf uvadj 100pf 1f 10f 10v 1f cer. 4.7f + + 0.01f 10k v cc 1000pf s4 + s4 ? s5 + s5 ? s6 ? s6 + v cc pllin pllfltr fcb nc nc nc ltc3731hg eain sgnd sense4 + sense4 ? sense5 + sense5 ? sense6 ? sense6 + run/ss i th i th uvadj clkout 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 pgood boost4 tg4 sw4 boost5 tg5 sw5 v dr bg4 pgnd bg5 bg6 sw6 tg6 boost6 phasmd sgnd2 1000pf 1000pf v in m10 x2 m11,12 d4 s4 + s4 ? l4 0.002 100pf 1.2k 2700pf 270pf 10pf 1000pf clkout clk1 uvadj pgood boost4 10 1000pf 0.1f 0.1f 0.1f boost5 boost6 v in m13 x2 m14,15 d5 s5 + s5 ? l5 0.002 v in m16 x2 m17,18 d6 s6 + s6 ? l6 0.002 v5 1f cer. 4.7f +
ltc3731h 0 3731hfb 3-phase boost converter. v in = 10v to 18v with 36v load dump, v out = 50v at 3a typical a pplica t ions v cc c1 1f 6.5v r4 0 r3 opt pllin pllfltr fcb nc nc nc ltc3731hg eain sgnd sense1 + sense1 ? sense2 + sense2 ? sense3 ? sense3 + run/ss i th uvadj clk 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 pgood boost1 tg1 sw1 boost2 tg2 sw2 v dr bg1 pgnd bg2 bg3 sw3 tg3 boost3 phasmd sgnd + c3 opt r7 665k c4 1000pf v out + r10 500 r11 500 r6 8.06k r1 10 r2 1m 1 2 8 5 4 s1 + s1 ? c5 1000pf r12 500 r13 500 s2 + s2 ? c6 1000pf c7 0.1f c53 1000pf r14 500 r15 500 run/ss v in + v in + s3 + s3 ? run/ss r16 10k c8 1000pf c9 220pf r17 121k r18 845k r30 opt is signal ground is power ground keep separate and refer to pcb layout checklist for routing information c1 4.7f q3 si7852dp l3 12h c in4 -c in6 : 10f, 50v x5r tdk c5750x5r1h106m c16-c26: 1f, 100v x7r taiyo yuden hmk432bj105km c17: 150f, 63v sanyo aluminum electrolytic 63mv150gx c20: 33f, 100v sanyo aluminum electrolytic 100cv33fs l1-l3: 12h sumida cdrh127/ld-120 r23 0.007 6.5v s3 + 3731h ta01 s3 ? q2 si7852dp l2 12h r23 0.007 s2 + s2 ? q1 si7852dp l1 12h d4 30bq060 d4 30bq060 d4 30bq060 v in + v in ? v out + 50v/3a v out ? v in + c in4 -c in6 10f 50v c16-c18, c20-c26 1f 100v c17 150f 63v + c20 33f 100v 10v to 18v with 36v load dump r23 0.007 s1 + s1 ? c19 1f 10v c18 1f 50v r5 249k in lt3010 shdn out v in + adj gnd v out +
ltc3731h 3731hfb p ackage descrip t ion g36 ssop 0204 0.09 ? 0.25 (.0035 ? .010) 0 ? 8 0.55 ? 0.95 (.022 ? .037) 5.00 ? 5.60** (.197 ? .221) 7.40 ? 8.20 (.291 ? .323) 1 2 3 4 5 6 7 8 9 10 11 12 14 15 16 17 18 13 12.50 ? 13.10* (.492 ? .516) 2526 22 21 20 19 2324 27282930313233343536 2.0 (.079) max 0.05 (.002) min 0.65 (.0256) bsc 0.22 ? 0.38 (.009 ? .015) typ millimeters (inches) dimensions do not include mold flash. mold flash shall not exceed .152mm (.006") per side dimensions do not include interlead flash. interlead flash shall not exceed .254mm (.010") per side * ** note: 1. controlling dimension: millimeters 2. dimensions are in 3. drawing not to scale 0.42 0.03 0.65 bsc 5.3 ? 5.7 7.8 ? 8.2 recommended solder pad layout 1.25 0.12 g package 36-lead plastic ssop (5.3mm) (reference ltc dwg # 05-08-1640)
ltc3731h 3731hfb p ackage descrip t ion 5.00 p 0.10 (4 sides) note: 1. drawing proposed to be a jedec package outline m0-220 variation whhd-(x) (to be approved) 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.40 p 0.10 31 1 2 32 bottom view?exposed pad 3.50 ref (4-sides) 3.45 p 0.10 3.45 p 0.10 0.75 p 0.05 r = 0.115 typ 0.25 p 0.05 (uh32) qfn 0406 rev d 0.50 bsc 0.200 ref 0.00 ? 0.05 0.70 p0.05 3.50 ref (4 sides) 4.10 p0.05 5.50 p0.05 0.25 p 0.05 package outline 0.50 bsc recommended solder pad layout apply solder mask to areas that are not soldered pin 1 notch r = 0.30 typ or 0.35 s 45 chamfer r = 0.05 typ 3.45 p 0.05 3.45 p 0.05 uh package 32-lead plastic qfn (5mm 5mm) (reference ltc dwg # 05-08-1693 rev d)
ltc3731h 3731hfb information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. r evision h is t ory rev date description page number b 5/10 uh package added. changes reflected throughout the data sheet 1 - 34 (revision history begins at rev b)
ltc3731h 3731hfb linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com ? linear technology corporation 2010 lt 0510 rev b ? printed in usa r ela t e d p ar t s typical a pplica t ion 1f v cc 1000pf s1 + s1 ? s2 + s2 ? s3 ? s3 + v cc pllin pllfltr fcb nc nc nc ltc3731hg eain sgnd sense1 + sense1 ? sense2 + sense2 ? sense3 ? sense3 + run/ss i th i th uvadj clk 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 pgood boost1 tg1 sw1 boost2 tg2 sw2 v dr bg1 pgnd bg2 bg3 sw3 tg3 boost3 phasmd sgnd 100pf short pllfltr to sgnd 20k 147k 10 v5 5v to 7v v in m1 m2 d1 s1 + s1 ? l1 0.003 0.01f 3.01k 10nf 100pf 1000pf 1f nc 3731h ta02 v in : 9v to 28v v out : 5v at 40a switching frequency: 225khz pgood 47k 1 1000pf 10f 0.1f v5 0.1f 0.1f v5 v5 v in m3 m4 d2 s2 + s2 ? l2 0.003 v in m5 m6 d3 s3 + s3 ? l3 0.003 47f 10v s3 c out v in 9v to 28v v out 5v at 40a + 4.7f 50v s6 c in 47f 35v s4 + c in : kemet t521x476m035ate070 s4 c out : sanyo 6tpe220mi s3 d1 to d3: diodes inc. b340a l1 to l3: 2.2h wurth 7443320220 m1, m3, m5: rjk0305dpb m2, m4, m6: rjk0330dpb v in 18k 12k part number description comments ltc3829 3-phase, single output, synchronous step-down controller with differential amp and dcr temperature compensation 4.5v v in 38v, 0.8v v out 5v, active voltage positioning, stage shedding ltc3856 2-phase, single output, synchronous step-down controller with differential amp and dcr temperature compensation 4.5v v in 38v, 0.8v v out 5v, active voltage positioning, stage shedding ltc3855 dual, multiphase, synchronous step-down dc/dc controller with differential amp and dcr temperature compensation phase-lockable fixed frequency 250khz to 770khz, 4.5v v in 38v, 0.8v v out 12v ltc3860 dual, multiphase, synchronous step-down dc/dc controller with differential amp and tri-state output drive operates with power blocks, drmos devices or external mosfets 3v v in 24v, t on(min) = 20ns ltc3853 triple output, multiphase synchronous step-down dc/dc controller, r sense or dcr current sensing and tracking phase-lockable fixed 250khz to 750khz frequency, 4v v in 24v, v out3 up to 13.5v ltc3850/ ltc3850-1/ ltc3850-2 dual 2-phase, high efficiency synchronous step-down dc/dc controller, r sense or dcr current sensing and tracking phase-lockable fixed 250khz to 780khz frequency, 4v v in 30v, 0.8v v out 5.25v

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